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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\yami\Documents\RVX32\impl\gwsynthesis\RVX32.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\yami\Documents\RVX32\src\RVX32.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NZ-LV1QN48C6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NZ-1</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Nov 29 14:47:26 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C C6/I5</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C C6/I5</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>1660</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>1024</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>42</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>234</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>1</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>rv_data_w_Z</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>rv32/data_w_s0/Q </td>
</tr>
<tr>
<td>n79_3</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>n79_s0/F </td>
</tr>
<tr>
<td>rv32/cpu_clk_exec</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec_s0/F </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>50.000(MHz)</td>
<td style="color: #FF0000;">47.680(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>n79_3</td>
<td>50.000(MHz)</td>
<td>62.680(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>rv32/cpu_clk_exec</td>
<td>50.000(MHz)</td>
<td>202.140(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of rv_data_w_Z!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>-2.425</td>
<td>9</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>rv_data_w_Z</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>rv_data_w_Z</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n79_3</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>n79_3</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>rv32/cpu_clk_exec</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>rv32/cpu_clk_exec</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-7.968</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_27_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>14.162</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-7.968</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_26_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>14.162</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-7.761</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_0_s104/D</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.597</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-7.551</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_30_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.745</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-7.507</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_7_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.700</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-7.500</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_29_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.693</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-7.486</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_11_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.680</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-7.486</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_5_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.680</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-7.486</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_1_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.680</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-7.448</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_10_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.642</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-7.448</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_3_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.642</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-7.447</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_24_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.640</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-7.447</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_18_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.640</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_25_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_22_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_21_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_20_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_19_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_13_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_4_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-7.221</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_2_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.414</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-7.219</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_9_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.412</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-7.219</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_0_s98/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.412</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-7.173</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs1_28_s5/RESET</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.366</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-7.171</td>
<td>GO_SP/sp_inst_0/DO[3]</td>
<td>rv32/rs2_19_s6/D</td>
<td>clk:[F]</td>
<td>n79_3:[R]</td>
<td>10.000</td>
<td>3.733</td>
<td>13.008</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-0.952</td>
<td>n180_s0/I0</td>
<td>GO_SP/sp_inst_0/WRE</td>
<td>rv_data_w_Z:[F]</td>
<td>clk:[F]</td>
<td>0.000</td>
<td>-3.205</td>
<td>2.330</td>
</tr>
<tr>
<td>2</td>
<td>0.427</td>
<td>rv32/rx32x/rd_write_0_s0/Q</td>
<td>rv32/REG_REG_0_0_s1/ADA[5]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.602</td>
</tr>
<tr>
<td>3</td>
<td>0.524</td>
<td>rv32/data_outr_13_s0/Q</td>
<td>data_outr_s2/D</td>
<td>n79_3:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>-2.095</td>
<td>2.649</td>
</tr>
<tr>
<td>4</td>
<td>0.579</td>
<td>rv32/PC_26_s0/Q</td>
<td>rv32/rs1_26_s13/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.579</td>
</tr>
<tr>
<td>5</td>
<td>0.709</td>
<td>rv32/rx32x/rd_write_0_s0/Q</td>
<td>rv32/REG_REG_0_0_s/ADA[5]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.885</td>
</tr>
<tr>
<td>6</td>
<td>0.710</td>
<td>data_pos_6_s1/Q</td>
<td>data_pos_6_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.710</td>
</tr>
<tr>
<td>7</td>
<td>0.710</td>
<td>rv32/PC_25_s0/Q</td>
<td>rv32/PC_25_s0/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.710</td>
</tr>
<tr>
<td>8</td>
<td>0.711</td>
<td>data_pos_2_s5/Q</td>
<td>data_pos_2_s5/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.711</td>
</tr>
<tr>
<td>9</td>
<td>0.711</td>
<td>data_pos_1_s5/Q</td>
<td>data_pos_1_s5/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.711</td>
</tr>
<tr>
<td>10</td>
<td>0.711</td>
<td>rv32/PC_6_s0/Q</td>
<td>rv32/PC_6_s0/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.711</td>
</tr>
<tr>
<td>11</td>
<td>0.712</td>
<td>data_pos_3_s5/Q</td>
<td>data_pos_3_s5/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.712</td>
</tr>
<tr>
<td>12</td>
<td>0.714</td>
<td>rv32/PC_3_s0/Q</td>
<td>rv32/PC_3_s0/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.714</td>
</tr>
<tr>
<td>13</td>
<td>0.717</td>
<td>rv32/rx32x/cpu_rw_bit_s1/Q</td>
<td>rv32/rx32x/cpu_rw_bit_s1/D</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.717</td>
</tr>
<tr>
<td>14</td>
<td>0.732</td>
<td>rv32/rx32x/rd_write_4_s0/Q</td>
<td>rv32/REG_REG_0_0_s1/ADA[9]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.907</td>
</tr>
<tr>
<td>15</td>
<td>0.732</td>
<td>rv32/rx32x/rd_write_3_s0/Q</td>
<td>rv32/REG_REG_0_0_s1/ADA[8]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.907</td>
</tr>
<tr>
<td>16</td>
<td>0.732</td>
<td>rv32/rx32x/rd_write_2_s0/Q</td>
<td>rv32/REG_REG_0_0_s1/ADA[7]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.907</td>
</tr>
<tr>
<td>17</td>
<td>0.732</td>
<td>rv32/rx32x/rd_write_3_s0/Q</td>
<td>rv32/REG_REG_0_0_s/ADA[8]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.907</td>
</tr>
<tr>
<td>18</td>
<td>0.732</td>
<td>data_bit_pos_3_s0/Q</td>
<td>data_bit_pos_3_s0/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.732</td>
</tr>
<tr>
<td>19</td>
<td>0.736</td>
<td>rv32/rx32x/rd_write_4_s0/Q</td>
<td>rv32/REG_REG_0_0_s/ADA[9]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>-0.070</td>
<td>0.911</td>
</tr>
<tr>
<td>20</td>
<td>0.837</td>
<td>rv32/PC_22_s0/Q</td>
<td>rv32/rs1_22_s13/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.837</td>
</tr>
<tr>
<td>21</td>
<td>0.839</td>
<td>rv32/PC_15_s0/Q</td>
<td>rv32/rs1_15_s13/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.839</td>
</tr>
<tr>
<td>22</td>
<td>0.899</td>
<td>rv32/rx32x/cpu_rw_bit_s1/Q</td>
<td>rv32/rx32x/cpu_jmp_bit_s0/CE</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>rv32/cpu_clk_exec:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.914</td>
</tr>
<tr>
<td>23</td>
<td>0.907</td>
<td>rv32/PC_5_s0/Q</td>
<td>rv32/rs1_5_s13/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.907</td>
</tr>
<tr>
<td>24</td>
<td>0.910</td>
<td>rv32/PC_16_s0/Q</td>
<td>rv32/rs1_16_s13/D</td>
<td>n79_3:[R]</td>
<td>n79_3:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.910</td>
</tr>
<tr>
<td>25</td>
<td>0.953</td>
<td>data_pos_3_s5/Q</td>
<td>data_pos_4_s5/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.953</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>6.824</td>
<td>8.074</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td>2</td>
<td>7.088</td>
<td>8.338</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td>3</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_18_s0</td>
</tr>
<tr>
<td>4</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_4_s0</td>
</tr>
<tr>
<td>5</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_28_s0</td>
</tr>
<tr>
<td>6</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_20_s0</td>
</tr>
<tr>
<td>7</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_19_s0</td>
</tr>
<tr>
<td>8</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_6_s0</td>
</tr>
<tr>
<td>9</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_7_s0</td>
</tr>
<tr>
<td>10</td>
<td>7.302</td>
<td>8.552</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>data_r_23_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.968</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.924</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_27_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.924</td>
<td>2.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_27_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>rv32/rs1_27_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_27_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>rv32/rs1_27_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 21.819%; route: 7.612, 53.748%; tC2Q: 3.460, 24.432%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.968</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.924</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_26_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.924</td>
<td>2.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" font-weight:bold;">rv32/rs1_26_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>rv32/rs1_26_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_26_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>rv32/rs1_26_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 21.819%; route: 7.612, 53.748%; tC2Q: 3.460, 24.432%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.761</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.359</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.598</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_0_s104</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.542</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.359</td>
<td>1.817</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R10C13[1][B]</td>
<td style=" font-weight:bold;">rv32/rs1_0_s104/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C13[1][B]</td>
<td>rv32/rs1_0_s104/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_0_s104</td>
</tr>
<tr>
<td>20.598</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R10C13[1][B]</td>
<td>rv32/rs1_0_s104</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.096, 22.769%; route: 7.041, 51.784%; tC2Q: 3.460, 25.446%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.551</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.507</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_30_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.507</td>
<td>1.971</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C6[0][B]</td>
<td style=" font-weight:bold;">rv32/rs1_30_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C6[0][B]</td>
<td>rv32/rs1_30_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_30_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C6[0][B]</td>
<td>rv32/rs1_30_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.481%; route: 7.195, 52.345%; tC2Q: 3.460, 25.173%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.507</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.462</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_7_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.462</td>
<td>1.926</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C8[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_7_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C8[2][A]</td>
<td>rv32/rs1_7_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_7_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R3C8[2][A]</td>
<td>rv32/rs1_7_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.554%; route: 7.150, 52.191%; tC2Q: 3.460, 25.255%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.500</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.455</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_29_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.455</td>
<td>1.919</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C11[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_29_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C11[2][A]</td>
<td>rv32/rs1_29_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_29_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C11[2][A]</td>
<td>rv32/rs1_29_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.565%; route: 7.143, 52.167%; tC2Q: 3.460, 25.267%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.486</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.441</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_11_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.441</td>
<td>1.905</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[1][A]</td>
<td style=" font-weight:bold;">rv32/rs1_11_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[1][A]</td>
<td>rv32/rs1_11_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_11_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C9[1][A]</td>
<td>rv32/rs1_11_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.589%; route: 7.130, 52.118%; tC2Q: 3.460, 25.293%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.486</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.441</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_5_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.441</td>
<td>1.905</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_5_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[2][A]</td>
<td>rv32/rs1_5_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_5_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C9[2][A]</td>
<td>rv32/rs1_5_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.589%; route: 7.130, 52.118%; tC2Q: 3.460, 25.293%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.486</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.441</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_1_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.441</td>
<td>1.905</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[1][B]</td>
<td style=" font-weight:bold;">rv32/rs1_1_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C9[1][B]</td>
<td>rv32/rs1_1_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_1_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C9[1][B]</td>
<td>rv32/rs1_1_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.589%; route: 7.130, 52.118%; tC2Q: 3.460, 25.293%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.404</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_10_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.404</td>
<td>1.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C10[1][B]</td>
<td style=" font-weight:bold;">rv32/rs1_10_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C10[1][B]</td>
<td>rv32/rs1_10_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_10_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C10[1][B]</td>
<td>rv32/rs1_10_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.651%; route: 7.092, 51.985%; tC2Q: 3.460, 25.363%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.404</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_3_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.404</td>
<td>1.868</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C10[1][A]</td>
<td style=" font-weight:bold;">rv32/rs1_3_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C10[1][A]</td>
<td>rv32/rs1_3_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_3_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C10[1][A]</td>
<td>rv32/rs1_3_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.651%; route: 7.092, 51.985%; tC2Q: 3.460, 25.363%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.447</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.402</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_24_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.402</td>
<td>1.866</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C8[0][A]</td>
<td style=" font-weight:bold;">rv32/rs1_24_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C8[0][A]</td>
<td>rv32/rs1_24_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_24_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R10C8[0][A]</td>
<td>rv32/rs1_24_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.654%; route: 7.090, 51.980%; tC2Q: 3.460, 25.366%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.447</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.402</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_18_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.402</td>
<td>1.866</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C9[1][A]</td>
<td style=" font-weight:bold;">rv32/rs1_18_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C9[1][A]</td>
<td>rv32/rs1_18_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_18_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R10C9[1][A]</td>
<td>rv32/rs1_18_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 22.654%; route: 7.090, 51.980%; tC2Q: 3.460, 25.366%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_25_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C10[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_25_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C10[2][A]</td>
<td>rv32/rs1_25_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_25_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R10C10[2][A]</td>
<td>rv32/rs1_25_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_22_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C7[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_22_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C7[2][A]</td>
<td>rv32/rs1_22_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_22_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C7[2][A]</td>
<td>rv32/rs1_22_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_21_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" font-weight:bold;">rv32/rs1_21_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>rv32/rs1_21_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_21_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>rv32/rs1_21_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_20_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C8[1][A]</td>
<td style=" font-weight:bold;">rv32/rs1_20_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C8[1][A]</td>
<td>rv32/rs1_20_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_20_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C8[1][A]</td>
<td>rv32/rs1_20_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_19_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_19_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>rv32/rs1_19_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_19_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>rv32/rs1_19_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_13_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[2][B]</td>
<td style=" font-weight:bold;">rv32/rs1_13_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C8[2][B]</td>
<td>rv32/rs1_13_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_13_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C8[2][B]</td>
<td>rv32/rs1_13_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_4_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C7[2][B]</td>
<td style=" font-weight:bold;">rv32/rs1_4_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C7[2][B]</td>
<td>rv32/rs1_4_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_4_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C7[2][B]</td>
<td>rv32/rs1_4_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.221</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.176</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_2_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.176</td>
<td>1.640</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td style=" font-weight:bold;">rv32/rs1_2_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>rv32/rs1_2_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_2_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R2C3[0][A]</td>
<td>rv32/rs1_2_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.036%; route: 6.864, 51.170%; tC2Q: 3.460, 25.794%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.219</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.174</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_9_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.174</td>
<td>1.638</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td style=" font-weight:bold;">rv32/rs1_9_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][A]</td>
<td>rv32/rs1_9_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_9_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C13[2][A]</td>
<td>rv32/rs1_9_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.039%; route: 6.862, 51.163%; tC2Q: 3.460, 25.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.219</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.174</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_0_s98</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.174</td>
<td>1.638</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][B]</td>
<td style=" font-weight:bold;">rv32/rs1_0_s98/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C13[2][B]</td>
<td>rv32/rs1_0_s98/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_0_s98</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C13[2][B]</td>
<td>rv32/rs1_0_s98</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.039%; route: 6.862, 51.163%; tC2Q: 3.460, 25.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.173</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>28.128</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_28_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>25.510</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C14[3][A]</td>
<td>rv32/rs1_0_s108/I1</td>
</tr>
<tr>
<td>26.536</td>
<td>1.026</td>
<td>tINS</td>
<td>FR</td>
<td>33</td>
<td>R2C14[3][A]</td>
<td style=" background: #97FFFF;">rv32/rs1_0_s108/F</td>
</tr>
<tr>
<td>28.128</td>
<td>1.592</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C10[0][A]</td>
<td style=" font-weight:bold;">rv32/rs1_28_s5/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C10[0][A]</td>
<td>rv32/rs1_28_s5/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs1_28_s5</td>
</tr>
<tr>
<td>20.955</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C10[0][A]</td>
<td>rv32/rs1_28_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.090, 23.118%; route: 6.816, 50.995%; tC2Q: 3.460, 25.887%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-7.171</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>27.770</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>20.598</td>
</tr>
<tr>
<td class="label">From</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs2_19_s6</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>32</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>18.222</td>
<td>3.460</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/DO[3]</td>
</tr>
<tr>
<td>20.677</td>
<td>2.455</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C16[1][B]</td>
<td>rv32/rs2isimm_s1/I0</td>
</tr>
<tr>
<td>21.709</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R4C16[1][B]</td>
<td style=" background: #97FFFF;">rv32/rs2isimm_s1/F</td>
</tr>
<tr>
<td>23.167</td>
<td>1.458</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R4C15[0][A]</td>
<td>rv32/n2149_s0/I3</td>
</tr>
<tr>
<td>24.199</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R4C15[0][A]</td>
<td style=" background: #97FFFF;">rv32/n2149_s0/F</td>
</tr>
<tr>
<td>26.671</td>
<td>2.472</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>rv32/n641_s0/I2</td>
</tr>
<tr>
<td>27.770</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">rv32/n641_s0/F</td>
</tr>
<tr>
<td>27.770</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" font-weight:bold;">rv32/rs2_19_s6/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>20.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>21.028</td>
<td>1.028</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>rv32/rs2_19_s6/CLK</td>
</tr>
<tr>
<td>20.998</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/rs2_19_s6</td>
</tr>
<tr>
<td>20.598</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[0][B]</td>
<td>rv32/rs2_19_s6</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-3.733</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.984, 20.672%; route: 3.778, 79.328%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.163, 24.316%; route: 6.385, 49.084%; tC2Q: 3.460, 26.599%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.028, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.952</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>12.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.282</td>
</tr>
<tr>
<td class="label">From</td>
<td>n180_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv_data_w_Z:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv_data_w_Z</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>7</td>
<td>R10C10[1][A]</td>
<td>rv32/data_w_s0/Q</td>
</tr>
<tr>
<td>11.032</td>
<td>1.032</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C16[0][B]</td>
<td style=" font-weight:bold;">n180_s0/I0</td>
</tr>
<tr>
<td>11.758</td>
<td>0.726</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R7C16[0][B]</td>
<td style=" background: #97FFFF;">n180_s0/F</td>
</tr>
<tr>
<td>12.330</td>
<td>0.572</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[2]</td>
<td style=" font-weight:bold;">GO_SP/sp_inst_0/WRE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.847</td>
<td>0.847</td>
<td>tINS</td>
<td>FF</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>13.205</td>
<td>2.358</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
<tr>
<td>13.235</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>GO_SP/sp_inst_0</td>
</tr>
<tr>
<td>13.282</td>
<td>0.047</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[2]</td>
<td>GO_SP/sp_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>3.205</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.000, 0.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.726, 31.160%; route: 0.572, 24.566%; tC2Q: 1.032, 44.274%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.847, 26.427%; route: 2.358, 73.573%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.427</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.285</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C3[2][A]</td>
<td>rv32/rx32x/rd_write_0_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R5C3[2][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_0_s0/Q</td>
</tr>
<tr>
<td>1.285</td>
<td>0.268</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s1/ADA[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.268, 44.611%; tC2Q: 0.333, 55.389%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.403</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.879</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/data_outr_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_outr_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C16[0][B]</td>
<td>rv32/data_outr_13_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R5C16[0][B]</td>
<td style=" font-weight:bold;">rv32/data_outr_13_s0/Q</td>
</tr>
<tr>
<td>1.325</td>
<td>0.238</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C17[2][A]</td>
<td>n321_s184/I1</td>
</tr>
<tr>
<td>1.881</td>
<td>0.556</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R5C17[2][A]</td>
<td style=" background: #97FFFF;">n321_s184/F</td>
</tr>
<tr>
<td>2.147</td>
<td>0.265</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][B]</td>
<td>n322_s26/I0</td>
</tr>
<tr>
<td>2.532</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][B]</td>
<td style=" background: #97FFFF;">n322_s26/F</td>
</tr>
<tr>
<td>2.532</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][A]</td>
<td>n322_s12/I1</td>
</tr>
<tr>
<td>2.630</td>
<td>0.098</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][A]</td>
<td style=" background: #97FFFF;">n322_s12/O</td>
</tr>
<tr>
<td>2.630</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][B]</td>
<td>n322_s5/I1</td>
</tr>
<tr>
<td>2.696</td>
<td>0.066</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R3C17[2][B]</td>
<td style=" background: #97FFFF;">n322_s5/O</td>
</tr>
<tr>
<td>2.696</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[1][B]</td>
<td>n322_s2/I0</td>
</tr>
<tr>
<td>2.762</td>
<td>0.066</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R3C17[1][B]</td>
<td style=" background: #97FFFF;">n322_s2/O</td>
</tr>
<tr>
<td>2.762</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[3][B]</td>
<td>n322_s0/I1</td>
</tr>
<tr>
<td>2.828</td>
<td>0.066</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R3C17[3][B]</td>
<td style=" background: #97FFFF;">n322_s0/O</td>
</tr>
<tr>
<td>3.403</td>
<td>0.575</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[0][A]</td>
<td style=" font-weight:bold;">data_outr_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[0][A]</td>
<td>data_outr_s2/CLK</td>
</tr>
<tr>
<td>2.879</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>data_outr_s2</td>
</tr>
<tr>
<td>2.879</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C19[0][A]</td>
<td>data_outr_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>2.095</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.237, 46.693%; route: 1.079, 40.725%; tC2Q: 0.333, 12.582%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.640%; route: 2.004, 70.360%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.579</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.333</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_26_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_26_s13</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[2][B]</td>
<td>rv32/PC_26_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>7</td>
<td>R8C11[2][B]</td>
<td style=" font-weight:bold;">rv32/PC_26_s0/Q</td>
</tr>
<tr>
<td>1.333</td>
<td>0.246</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">rv32/rs1_26_s13/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>rv32/rs1_26_s13/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>rv32/rs1_26_s13</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.246, 42.477%; tC2Q: 0.333, 57.523%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.568</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C3[2][A]</td>
<td>rv32/rx32x/rd_write_0_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R5C3[2][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_0_s0/Q</td>
</tr>
<tr>
<td>1.568</td>
<td>0.551</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s/ADA[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.551, 62.319%; tC2Q: 0.333, 37.681%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.710</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.849</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_pos_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_pos_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C16[1][A]</td>
<td>data_pos_6_s1/CLK</td>
</tr>
<tr>
<td>3.182</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R10C16[1][A]</td>
<td style=" font-weight:bold;">data_pos_6_s1/Q</td>
</tr>
<tr>
<td>3.187</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C16[1][A]</td>
<td>n385_s1/I3</td>
</tr>
<tr>
<td>3.559</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R10C16[1][A]</td>
<td style=" background: #97FFFF;">n385_s1/F</td>
</tr>
<tr>
<td>3.559</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R10C16[1][A]</td>
<td style=" font-weight:bold;">data_pos_6_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C16[1][A]</td>
<td>data_pos_6_s1/CLK</td>
</tr>
<tr>
<td>2.849</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R10C16[1][A]</td>
<td>data_pos_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.640%; route: 2.004, 70.360%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.640%; route: 2.004, 70.360%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.710</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.464</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_25_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/PC_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C13[0][A]</td>
<td>rv32/PC_25_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R3C13[0][A]</td>
<td style=" font-weight:bold;">rv32/PC_25_s0/Q</td>
</tr>
<tr>
<td>1.092</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C13[0][A]</td>
<td>rv32/n1037_s1/I1</td>
</tr>
<tr>
<td>1.464</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R3C13[0][A]</td>
<td style=" background: #97FFFF;">rv32/n1037_s1/F</td>
</tr>
<tr>
<td>1.464</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C13[0][A]</td>
<td style=" font-weight:bold;">rv32/PC_25_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C13[0][A]</td>
<td>rv32/PC_25_s0/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C13[0][A]</td>
<td>rv32/PC_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.548</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.836</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_pos_2_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_pos_2_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.836</td>
<td>1.992</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>data_pos_2_s5/CLK</td>
</tr>
<tr>
<td>3.170</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R9C15[0][A]</td>
<td style=" font-weight:bold;">data_pos_2_s5/Q</td>
</tr>
<tr>
<td>3.176</td>
<td>0.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>n389_s0/I0</td>
</tr>
<tr>
<td>3.548</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td style=" background: #97FFFF;">n389_s0/F</td>
</tr>
<tr>
<td>3.548</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td style=" font-weight:bold;">data_pos_2_s5/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.836</td>
<td>1.992</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>data_pos_2_s5/CLK</td>
</tr>
<tr>
<td>2.836</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C15[0][A]</td>
<td>data_pos_2_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.770%; route: 1.992, 70.230%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.770%; route: 1.992, 70.230%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.554</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_pos_1_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_pos_1_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[1][A]</td>
<td>data_pos_1_s5/CLK</td>
</tr>
<tr>
<td>3.176</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R8C17[1][A]</td>
<td style=" font-weight:bold;">data_pos_1_s5/Q</td>
</tr>
<tr>
<td>3.182</td>
<td>0.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[1][A]</td>
<td>n390_s2/I0</td>
</tr>
<tr>
<td>3.554</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C17[1][A]</td>
<td style=" background: #97FFFF;">n390_s2/F</td>
</tr>
<tr>
<td>3.554</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C17[1][A]</td>
<td style=" font-weight:bold;">data_pos_1_s5/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C17[1][A]</td>
<td>data_pos_1_s5/CLK</td>
</tr>
<tr>
<td>2.843</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C17[1][A]</td>
<td>data_pos_1_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.465</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/PC_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C12[0][A]</td>
<td>rv32/PC_6_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R3C12[0][A]</td>
<td style=" font-weight:bold;">rv32/PC_6_s0/Q</td>
</tr>
<tr>
<td>1.093</td>
<td>0.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C12[0][A]</td>
<td>rv32/n1056_s3/I0</td>
</tr>
<tr>
<td>1.465</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R3C12[0][A]</td>
<td style=" background: #97FFFF;">rv32/n1056_s3/F</td>
</tr>
<tr>
<td>1.465</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C12[0][A]</td>
<td style=" font-weight:bold;">rv32/PC_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C12[0][A]</td>
<td>rv32/PC_6_s0/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C12[0][A]</td>
<td>rv32/PC_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.712</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.555</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_pos_3_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_pos_3_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td>data_pos_3_s5/CLK</td>
</tr>
<tr>
<td>3.176</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R10C17[0][A]</td>
<td style=" font-weight:bold;">data_pos_3_s5/Q</td>
</tr>
<tr>
<td>3.183</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td>n388_s2/I0</td>
</tr>
<tr>
<td>3.555</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td style=" background: #97FFFF;">n388_s2/F</td>
</tr>
<tr>
<td>3.555</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td style=" font-weight:bold;">data_pos_3_s5/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td>data_pos_3_s5/CLK</td>
</tr>
<tr>
<td>2.843</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R10C17[0][A]</td>
<td>data_pos_3_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.714</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.467</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/PC_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C13[1][A]</td>
<td>rv32/PC_3_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>R2C13[1][A]</td>
<td style=" font-weight:bold;">rv32/PC_3_s0/Q</td>
</tr>
<tr>
<td>1.095</td>
<td>0.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C13[1][A]</td>
<td>rv32/n1059_s1/I2</td>
</tr>
<tr>
<td>1.467</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R2C13[1][A]</td>
<td style=" background: #97FFFF;">rv32/n1059_s1/F</td>
</tr>
<tr>
<td>1.467</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R2C13[1][A]</td>
<td style=" font-weight:bold;">rv32/PC_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C13[1][A]</td>
<td>rv32/PC_3_s0/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R2C13[1][A]</td>
<td>rv32/PC_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.717</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.401</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.684</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/cpu_rw_bit_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rx32x/cpu_rw_bit_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td>rv32/rx32x/cpu_rw_bit_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>20</td>
<td>R9C2[1][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/cpu_rw_bit_s1/Q</td>
</tr>
<tr>
<td>1.029</td>
<td>0.012</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td>rv32/rx32x/n1254_s4/I1</td>
</tr>
<tr>
<td>1.401</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td style=" background: #97FFFF;">rv32/rx32x/n1254_s4/F</td>
</tr>
<tr>
<td>1.401</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/cpu_rw_bit_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td>rv32/rx32x/cpu_rw_bit_s1/CLK</td>
</tr>
<tr>
<td>0.684</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C2[1][A]</td>
<td>rv32/rx32x/cpu_rw_bit_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 51.873%; route: 0.012, 1.646%; tC2Q: 0.333, 46.481%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.732</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C3[1][B]</td>
<td>rv32/rx32x/rd_write_4_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R7C3[1][B]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_4_s0/Q</td>
</tr>
<tr>
<td>1.591</td>
<td>0.574</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s1/ADA[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.574, 63.259%; tC2Q: 0.333, 36.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.732</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C3[0][A]</td>
<td>rv32/rx32x/rd_write_3_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R5C3[0][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_3_s0/Q</td>
</tr>
<tr>
<td>1.591</td>
<td>0.574</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s1/ADA[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.574, 63.259%; tC2Q: 0.333, 36.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.732</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C3[0][B]</td>
<td>rv32/rx32x/rd_write_2_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R5C3[0][B]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_2_s0/Q</td>
</tr>
<tr>
<td>1.591</td>
<td>0.574</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s1/ADA[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[0]</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.574, 63.259%; tC2Q: 0.333, 36.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.732</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C3[0][A]</td>
<td>rv32/rx32x/rd_write_3_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R5C3[0][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_3_s0/Q</td>
</tr>
<tr>
<td>1.591</td>
<td>0.574</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s/ADA[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.574, 63.259%; tC2Q: 0.333, 36.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.732</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.581</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.849</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_bit_pos_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_bit_pos_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C17[1][A]</td>
<td>data_bit_pos_3_s0/CLK</td>
</tr>
<tr>
<td>3.182</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R7C17[1][A]</td>
<td style=" font-weight:bold;">data_bit_pos_3_s0/Q</td>
</tr>
<tr>
<td>3.187</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R7C17[1][A]</td>
<td>n315_s/I1</td>
</tr>
<tr>
<td>3.581</td>
<td>0.394</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C17[1][A]</td>
<td style=" background: #97FFFF;">n315_s/SUM</td>
</tr>
<tr>
<td>3.581</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][A]</td>
<td style=" font-weight:bold;">data_bit_pos_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C17[1][A]</td>
<td>data_bit_pos_3_s0/CLK</td>
</tr>
<tr>
<td>2.849</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C17[1][A]</td>
<td>data_bit_pos_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.640%; route: 2.004, 70.360%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.394, 53.821%; route: 0.005, 0.645%; tC2Q: 0.333, 45.534%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.640%; route: 2.004, 70.360%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.736</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.595</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.859</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/rd_write_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C3[1][B]</td>
<td>rv32/rx32x/rd_write_4_s0/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R7C3[1][B]</td>
<td style=" font-weight:bold;">rv32/rx32x/rd_write_4_s0/Q</td>
</tr>
<tr>
<td>1.595</td>
<td>0.578</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td style=" font-weight:bold;">rv32/REG_REG_0_0_s/ADA[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s/CLKA</td>
</tr>
<tr>
<td>0.784</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
<tr>
<td>0.859</td>
<td>0.075</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R6[1]</td>
<td>rv32/REG_REG_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.070</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.578, 63.411%; tC2Q: 0.333, 36.589%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.837</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_22_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_22_s13</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C14[2][B]</td>
<td>rv32/PC_22_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R4C14[2][B]</td>
<td style=" font-weight:bold;">rv32/PC_22_s0/Q</td>
</tr>
<tr>
<td>1.591</td>
<td>0.504</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C15[1][A]</td>
<td style=" font-weight:bold;">rv32/rs1_22_s13/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C15[1][A]</td>
<td>rv32/rs1_22_s13/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C15[1][A]</td>
<td>rv32/rs1_22_s13</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.504, 60.176%; tC2Q: 0.333, 39.824%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.839</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.593</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_15_s13</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C14[2][B]</td>
<td>rv32/PC_15_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R10C14[2][B]</td>
<td style=" font-weight:bold;">rv32/PC_15_s0/Q</td>
</tr>
<tr>
<td>1.593</td>
<td>0.506</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C14[1][B]</td>
<td style=" font-weight:bold;">rv32/rs1_15_s13/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C14[1][B]</td>
<td>rv32/rs1_15_s13/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C14[1][B]</td>
<td>rv32/rs1_15_s13</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.506, 60.288%; tC2Q: 0.333, 39.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.899</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.598</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.699</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/rx32x/cpu_rw_bit_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rx32x/cpu_jmp_bit_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>rv32/cpu_clk_exec:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[1][A]</td>
<td>rv32/rx32x/cpu_rw_bit_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>20</td>
<td>R9C2[1][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/cpu_rw_bit_s1/Q</td>
</tr>
<tr>
<td>1.598</td>
<td>0.581</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[0][A]</td>
<td style=" font-weight:bold;">rv32/rx32x/cpu_jmp_bit_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>rv32/cpu_clk_exec</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>72</td>
<td>R9C11[1][B]</td>
<td>rv32/cpu_clk_exec_s0/F</td>
</tr>
<tr>
<td>0.684</td>
<td>0.684</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[0][A]</td>
<td>rv32/rx32x/cpu_jmp_bit_s0/CLK</td>
</tr>
<tr>
<td>0.699</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C2[0][A]</td>
<td>rv32/rx32x/cpu_jmp_bit_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.581, 63.544%; tC2Q: 0.333, 36.456%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.684, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.907</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.661</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_5_s13</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C11[1][A]</td>
<td>rv32/PC_5_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R2C11[1][A]</td>
<td style=" font-weight:bold;">rv32/PC_5_s0/Q</td>
</tr>
<tr>
<td>1.661</td>
<td>0.574</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C11[0][B]</td>
<td style=" font-weight:bold;">rv32/rs1_5_s13/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C11[0][B]</td>
<td>rv32/rs1_5_s13/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C11[0][B]</td>
<td>rv32/rs1_5_s13</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.574, 63.259%; tC2Q: 0.333, 36.741%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.910</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.664</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>rv32/PC_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>rv32/rs1_16_s13</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>n79_3:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>n79_3:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C13[2][A]</td>
<td>rv32/PC_16_s0/CLK</td>
</tr>
<tr>
<td>1.087</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R10C13[2][A]</td>
<td style=" font-weight:bold;">rv32/PC_16_s0/Q</td>
</tr>
<tr>
<td>1.664</td>
<td>0.577</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C14[1][B]</td>
<td style=" font-weight:bold;">rv32/rs1_16_s13/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>n79_3</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>271</td>
<td>R10C19[0][A]</td>
<td>n79_s0/F</td>
</tr>
<tr>
<td>0.754</td>
<td>0.754</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C14[1][B]</td>
<td>rv32/rs1_16_s13/CLK</td>
</tr>
<tr>
<td>0.754</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C14[1][B]</td>
<td>rv32/rs1_16_s13</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.577, 63.366%; tC2Q: 0.333, 36.634%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.754, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.953</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.795</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>data_pos_3_s5</td>
</tr>
<tr>
<td class="label">To</td>
<td>data_pos_4_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C17[0][A]</td>
<td>data_pos_3_s5/CLK</td>
</tr>
<tr>
<td>3.176</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>6</td>
<td>R10C17[0][A]</td>
<td style=" font-weight:bold;">data_pos_3_s5/Q</td>
</tr>
<tr>
<td>3.423</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R10C17[0][B]</td>
<td>n387_s1/I1</td>
</tr>
<tr>
<td>3.795</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R10C17[0][B]</td>
<td style=" background: #97FFFF;">n387_s1/F</td>
</tr>
<tr>
<td>3.795</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R10C17[0][B]</td>
<td style=" font-weight:bold;">data_pos_4_s5/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR6[E]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>56</td>
<td>IOR6[E]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>2.843</td>
<td>1.998</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R10C17[0][B]</td>
<td>data_pos_4_s5/CLK</td>
</tr>
<tr>
<td>2.843</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R10C17[0][B]</td>
<td>data_pos_4_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 39.046%; route: 0.247, 25.967%; tC2Q: 0.333, 34.987%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 29.705%; route: 1.998, 70.295%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.824</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.074</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>GO_SP/sp_inst_0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.836</td>
<td>1.992</td>
<td>tNET</td>
<td>RR</td>
<td>GO_SP/sp_inst_0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.088</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.338</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>rv32/REG_REG_0_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.762</td>
<td>3.778</td>
<td>tNET</td>
<td>FF</td>
<td>rv32/REG_REG_0_0_s1/CLKB</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>23.100</td>
<td>2.256</td>
<td>tNET</td>
<td>RR</td>
<td>rv32/REG_REG_0_0_s1/CLKB</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_18_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_18_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_18_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_4_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_4_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_4_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_28_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_28_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_28_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_20_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_20_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_20_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_19_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_19_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_19_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_6_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_7_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>7.302</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>8.552</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>data_r_23_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>14.297</td>
<td>3.313</td>
<td>tNET</td>
<td>FF</td>
<td>data_r_23_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>22.849</td>
<td>2.004</td>
<td>tNET</td>
<td>RR</td>
<td>data_r_23_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>271</td>
<td>n79_3</td>
<td>-3.604</td>
<td>1.445</td>
</tr>
<tr>
<td>145</td>
<td>rs2_0_6</td>
<td>2.548</td>
<td>2.650</td>
</tr>
<tr>
<td>72</td>
<td>cpu_clk_exec</td>
<td>6.044</td>
<td>1.078</td>
</tr>
<tr>
<td>56</td>
<td>clk_d</td>
<td>-0.393</td>
<td>3.778</td>
</tr>
<tr>
<td>54</td>
<td>data_bit_pos[0]</td>
<td>9.583</td>
<td>1.707</td>
</tr>
<tr>
<td>47</td>
<td>data_bit_pos[1]</td>
<td>8.892</td>
<td>3.456</td>
</tr>
<tr>
<td>44</td>
<td>cpu_jmp_bit_Z</td>
<td>15.053</td>
<td>2.322</td>
</tr>
<tr>
<td>41</td>
<td>data_bit_pos[2]</td>
<td>10.406</td>
<td>1.667</td>
</tr>
<tr>
<td>41</td>
<td>instr_reg[31]</td>
<td>6.319</td>
<td>1.812</td>
</tr>
<tr>
<td>36</td>
<td>n1122_3</td>
<td>11.385</td>
<td>1.387</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R2C2</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C6</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C9</td>
<td>100.00%</td>
</tr>
<tr>
<td>R3C18</td>
<td>100.00%</td>
</tr>
<tr>
<td>R3C19</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C7</td>
<td>100.00%</td>
</tr>
<tr>
<td>R10C18</td>
<td>100.00%</td>
</tr>
<tr>
<td>R10C19</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C4</td>
<td>100.00%</td>
</tr>
<tr>
<td>R3C6</td>
<td>100.00%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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